University of Strathclyde website
Digital Collections - University of Strathclyde Library
Search Results Previous Searches E-Shelf
Login End Session
Search 'System Number= 000004676' in 'General Silo' Collection [ Sorted by: Name/Title ] Refine search
Table view Full view
Record 1 of 1 1
Add to E-Shelf
e-item icon
PDF of thesis T14448 PDF of thesis T14448 - (1 M)
Title FPGA implementation of adaptive filters / by Michael N. Hanson.
Name Hanson, Michael N. .
Abstract Adaptive signal processing is an important topic of research covering many application areas such as audio signal processing, radar, wireless communications and control systems. In the context of wireless communications, the impulse response of the channel can vary rapidly with respect to time. Fast adaptive filtering algorithms are required in order to perform equalization of such channels. The two algorithms predominantly used in practice are variants of Least Mean Squares (LMS) and Recursive Least Squares (RLS) algorithms. LMS algorithms are more straightforward to implement however, RLS algorithms offer increased performance at the expense of greater complexity. For very high throughput operation, dedicated hardware is required to keep up with the incoming sampling rate. Field Programmable Gate Arrays (FPGAs) can provide superior performance both in terms of power utilization and throughput, when compared to Graphic Processor Unit (GPU) or Digital Signal Processor (DSP) implementation. However, despite the potential performance advantage, FPGA implementation progress has been limited by the difficulty of programming such devices. This motivates the development of software allowing the user to program FPGAs in a more straightforward manner than direct low-level programming. The first part of the following work seeks to alleviate this via means of a high abstraction level Intellectual Property (IP) core for both the classic LMS algorithm, and the Normalized LMS (NLMS) algorithm. High level parameters allow the user to trade resource utilization against throughput, choosing fully parallel, serial or partly-serial architectures. In the second part of this work, a survey is presented on the implementation of the QR Decomposition RLS (QRD-RLS) algorithm. Discussion is given on the numerical performance, cost and throughput of different architectures, with particular
Abstract detail presented on the Givens based systolic array architecture.
Publication date 2016.
Name University of Strathclyde. Dept. of Electronic and Electrical Engineering.
Thesis note Thesis M. Phil University of Strathclyde 2016 T14448

Powered by Digitool Contact us Electronic Library Services Library Home